# New Microcode for Intel CPUs.

## Dlareh

For those of you that don't follow http://planet.gentoo.org , Intel recently released new CPU microcode and r3pek blogged a mini-howto :

If you want to update CPU's microcode just do this:

```
emerge microcode-ctl

rc-update add microcode_ctl boot

wget http://urbanmyth.org/microcode/ucode/intel-ia32microcode-29Aug2005.txt.bz2

bunzip2 intel-ia32microcode-29Aug2005.txt.bz2

cp intel-ia32microcode-29Aug2005.txt /etc/microcode.dat

/etc/init.d/microcode_ctl start
```

 After this simple steps, your should be ready to go with the new microcode. Don't forget that to be able to update your microcode you have to have that option enabled on the kernel:

```
 -> Processor type and features

 /dev/cpu/microcode - Intel IA32 CPU microcode support
```

 Also, the new microcode that is uploaded to the CPU, doesn't get "saved", that's why you have to add microcode_ctl as a service, so it can upload the microcode to the CPU every boot.

 To confirm that everything went fine after run the init script run this command:

```
dmesg | tail
```

 If you have something like this in the result everything is fine and you have the new microcode running:

```
microcode: CPU0 updated from revision 0x17 to 0x18, date = 10172004
```

... and I got this on my pentium-m 1200mhz :

```
microcode: CPU0 updated from revision 0x5 to 0x7, date = 11092004
```

Post yours, if you would... I'm idly curious.

----------

## dpetka2001

so from the mini-howto I've read that microcode is something like a firmware for the CPU...though there isn't any changelog so we have to use it on our own risk...did you notice any improvement with your CPU?? could you share with us your observations overall if any?? thanks in advance...

----------

## Jeremy_Z

Yes, is there any use of doing that ? Well i guess the update has a reason, too bad it is not mentioned.

----------

## -Rick-

 *Jeremy_Z wrote:*   

> Yes, is there any use of doing that ? Well i guess the update has a reason, too bad it is not mentioned.

 

Maybe it secretly adds DRM? Who knows... :Wink: 

----------

## a2gentoo

This sounds like a neat idea. But....

What is in it for me?

Does it improve performance, power management? Make the kernel more stable?

Also. How is the firmware needed to be reloaded EVERY reboot. The old frimware doesnt. Something sounds odd.

Not that I am against this whole idea. I just dont understand "what is in it for me".

----------

## Jeremy_Z

The "old" one is there already so not need to load it i suppose.

----------

## NewBlackDak

CPU microcode isn't flash updateable, so you have to load it with software.

----------

## roderick

I'm going to try it tonight.

Has anyone else tried this yet? Did it improve anything or make any difference?

I have a Acer Aspire 1414WLCi notebook. It's a Pentium Celeron M (1.3GHz). 

I'll followup with my results.

Here's my cpuinfo currently:

```
fortune ~ # cat /proc/cpuinfo

processor       : 0

vendor_id       : GenuineIntel

cpu family      : 6

model           : 13

model name      : Intel(R) Celeron(R) M processor         1.30GHz

stepping        : 8

cpu MHz         : 1298.952

cache size      : 1024 KB

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 2

wp              : yes

flags           : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss tm pbe nx

bogomips        : 2564.09

```

----------

## ripper2256

 *Quote:*   

> Does it improve performance, power management? Make the kernel more stable? 

 

That's hard to tell, 'cause intel released no changelog  :Sad: 

To quote Carlos Silvia:  *Quote:*   

> a microcode update doesn't mean more performance, so don't yell at me because of this, I'm just a messenger 

 

But I will try and see if something cool happens  :Wink: 

----------

## pijalu

seems old news here

```

microcode: CPU0 already at revision 0x20 (current=0x20)

microcode: No new microcode data for CPU0

```

 :Cool: 

----------

## roderick

Ok,

Here's what I get after installing and updating the .dat file:

```
Sep 16 13:24:34 fortune IA-32 Microcode Update Driver: v1.14 <tigran@veritas.com>

Sep 16 13:24:34 fortune microcode: CPU0 updated from revision 0x0 to 0x20, date = 07222004

```

So, I got a major revision bump. Not sure how this will impact me.

I'll see if I notice any difference in performance.

Here's my new cpuinfo:

```
processor       : 0

vendor_id       : GenuineIntel

cpu family      : 6

model           : 13

model name      : Intel(R) Celeron(R) M processor         1.30GHz

stepping        : 8

cpu MHz         : 1299.397

cache size      : 1024 KB

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 2

wp              : yes

flags           : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca c     mov pat clflush dts acpi mmx fxsr sse sse2 ss tm pbe nx

bogomips        : 2564.09

```

Some differences.

This line changed: cpu MHz         : 1299.397

----------

## hans0r

```
 microcode: CPU0 updated from revision 0x5 to 0x7, date = 11092004 
```

```

processor       : 0

vendor_id       : GenuineIntel

cpu family      : 6

model           : 9

model name      : Intel(R) Pentium(R) M processor 1500MHz

stepping        : 5

cpu MHz         : 600.111

cache size      : 1024 KB

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 2

wp              : yes

flags           : fpu vme de pse tsc msr mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 tm pbe est tm2

bogomips        : 1201.83

```

no noticeable changes so far

----------

## roderick

Yeah, my cpuinfo changed back to the 1298 from 1299. Must be a slight variation in clock speed of CPU, so the microcode had no impact on that specifically.

Didn't seem to break anything. Haven't noticed any other differences.

Gee, wish intel would of published something of a change log.

----------

## pijalu

 *roderick wrote:*   

> ...
> 
> Gee, wish intel would of published something of a change log.

 

Like: Fixed all these undocumented bugs ? don't think they will   :Laughing: 

----------

## ripper2256

```
microcode: CPU0 updated from revision 0x5 to 0x7, date = 11092004
```

Hmm, everything works fine so far... I don't notice any difference...

Well, at leasts, it's kind of cool, to update the microcode of your own cpu... Yeah, ok, to be honest, I think this was a waste of time, the only thing i learnd here, is what a microcode is and what it is for.

----------

## ehatherley

Here's the line from an article written for linux-mag.com by one of the authors of the driver:

 *Quote:*   

> The Linux Microcode Update Driver      
> 
> Gearheads  
> 
> Written by Tigran Aivazian     
> ...

 

Presumably there is something in the official Intel literature as well, since it is referenced at the end of the article. Browsing around the Intel website turns up Intel® Pentium® 4 Processor Technical Documents. If you look at the "Specification Update" document, it has a whole table of things that "don't work as expected"; some software, some hardware. Some are 'fixed' others will never be fixed, presumably because they don't expect it to cause problems. Most of the 'bugs' are way out on the fringes where most code will never go.

To me it looks like these 'microcode updates' are not performance related but rather fixes for weird bugs. And I suspect that the microcode update files get bigger mostly because Intel brings out new processors. Notice that the update is a 'one-size-fits-all' sort of thing; Pentium Pro right up to P4! So installing it may not make your machine or code run faster, just more reliably!  :Smile: 

But does anyone remember how slow Intel was to admit that there was a problem with the math in some versions of the Pentium Pro? (Thats the fdiv_bug referenced in code in some of the previous posts)

See also:

http://www.techweb.com/wire/news/1997/11/1110intpent.html

Page32

Intel Microcode Update Utility for Linux

Seems rather odd to me, keeping something you mean to be taken seriously on a website called "UrbanMyth.org".   :Very Happy: 

----------

## Mark Clegg

On my Toshiba Satellite 1900/305 - P4 2.4GHz

IA-32 Microcode Update Driver: v1.14 <tigran@veritas.com>

microcode: CPU0 updated from revision 0x24 to 0x37, date = 06042003

----------

## anxt

```
microcode: CPU0 already at revision 0x12 (current=0x12)

microcode: No new microcode data for CPU0
```

```

processor       : 0

vendor_id       : GenuineIntel

cpu family      : 15

model           : 4

model name      : Intel(R) Pentium(R) 4 CPU 3.00GHz

stepping        : 1

cpu MHz         : 3008.929

cache size      : 1024 KB

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 5

wp              : yes

flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni monitor ds_cpl cid xtpr

bogomips        : 6019.04
```

----------

## Mimamau

```
microcode: CPU0 already at revision 0xc (current=0xc)

microcode: No new microcode data for CPU0
```

```
processor       : 0

vendor_id       : GenuineIntel

cpu family      : 6

model           : 8

model name      : Pentium III (Coppermine)

stepping        : 6

cpu MHz         : 696.979

cache size      : 256 KB

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 2

wp              : yes

flags           : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 mmx fxsr sse

bogomips        : 1376.25
```

----------

## voidengineer

Microcode is something that is generally used in CISC designes to tell a processor exactly how to execute an instruction, which may or may not take more than one clock cycle to achieve the desired results. For example the complexity of a multiplication instruction is controlled by the microcode which controls the ALU (arithmatic logic unit). In a way the microcode behaves like the code you might use to control a FPGA (field programmable gate array) in order to get the gates (logical building blocks) to work in a certain way to achieve a desired result. 

RISC systems, on the other hand, seek to improve performance by reducing the number of clock cycles required to perform tasks. They have small sets of simplified instructions, doing away with microcode altogether in most cases. While this means that tasks require more instructions, instructions are all of the same length and usually require only one clock cycle to complete. Because of this, RISC systems are capable of processing instructions in parallel in a process called pipelining. The CPU works on more than one instruction at once by starting the second instruction before it completes the first one. This greatly increases throughput and makes RISC systems substantially faster than their CISC counterparts. 

Anyways this is by no means the end all and be all of microcode, but perhaps it might shine a light on the subject.

----------

## pjv

consider this a calculated but totally unproved guess: Would Apple's switch to Intel processors have anything to do with it?

----------

## Dlareh

 *pjv wrote:*   

> consider this a calculated but totally unproved guess: Would Apple's switch to Intel processors have anything to do with it?

 

nyet, zero, zilch, nada, wouldn't make any sense whatsoever

----------

## codergeek42

 *Quote:*   

> microcode: CPU0 updated from revision 0xb to 0xc, date = 04212005

 Shweet.

```
processor       : 0

vendor_id       : GenuineIntel

cpu family      : 15

model           : 3

model name      : Intel(R) Pentium(R) 4 CPU 2.40GHz

stepping        : 3

cpu MHz         : 2412.308

cache size      : 1024 KB

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 5

wp              : yes

flags           : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni monitor ds_cpl cid

bogomips        : 4830.78
```

----------

## JSharku

EDIT: Seems I spoke too soon about the PentiumPro being dumped, although there's no difference between the microcode.dat that comes with portage and the recently released one:

With "old" microcode.dat

```

microcode: CPU1 updated from revision 0xd1 to 0xd2, date = 02181998

microcode: CPU0 updated from revision 0xd1 to 0xd2, date = 02181998

```

With "new" microcode.dat

```

microcode: CPU0 already at revision 0xd2 (current=0xd2)

microcode: CPU1 already at revision 0xd2 (current=0xd2)

microcode: No new microcode data for CPU1

microcode: No new microcode data for CPU0

```

Sharku

----------

## Cr0t

4x Pentium Pro 200MHz

```
microcode: CPU0 already at revision 0xc6 (current=0xc6)

microcode: CPU1 already at revision 0xc6 (current=0xc6)

microcode: CPU3 already at revision 0xc6 (current=0xc6)

microcode: No new microcode data for CPU3

microcode: No new microcode data for CPU0

microcode: CPU2 updated from revision 0xd1 to 0xd2, date = 02181998 

microcode: No new microcode data for CPU1
```

----------

## jakertberry

Pentium 4 3.0GHz with HT:

```
microcode: CPU0 updated from revision 0x13 to 0x17, date = 04212005

microcode: CPU1 updated from revision 0x13 to 0x17, date = 04212005
```

----------

## acoul

 *Quote:*   

> 
> 
> microcode: CPU0 updated from revision 0x0 to 0x12, date = 11222004
> 
> processor       : 0
> ...

 

 *Quote:*   

> 
> 
> microcode: CPU0 updated from revision 0x13 to 0x17, date = 04212005
> 
> processor       : 0
> ...

 

 *Quote:*   

> 
> 
> microcode: CPU0 updated from revision 0x5 to 0x12, date = 11222004
> 
> processor       : 0
> ...

 

 *Quote:*   

> 
> 
> microcode: CPU0 already at revision 0x39 (current=0x39)
> 
> microcode: No new microcode data for CPU0
> ...

 

 *Quote:*   

> 
> 
> microcode: CPU0 already at revision 0xd (current=0xd)
> 
> microcode: No new microcode data for CPU0
> ...

 

----------

## DarkFoon

```
microcode: CPU0 updated from revision 0x0 to 0x2a, date = 05121999

processor   : 0

vendor_id   : GenuineIntel

cpu family   : 6

model      : 5

model name   : Pentium II (Deschutes)

stepping   : 2

cpu MHz      : 300.818

cache size   : 512 KB

fdiv_bug   : no

hlt_bug      : no

f00f_bug   : no

coma_bug   : no

fpu      : yes

fpu_exception   : yes

cpuid level   : 2

wp      : yes

flags      : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 mmx fxsr

bogomips   : 602.07
```

out of curiosity, where could I find information regarding those flags? I recognize a few; I wonder what the rest mean.

----------

## ehatherley

For those interested in an MS Windows hacker's slant on the microcode update issue check Microcode updates - UPDATE.SYS. These guys are 'rolling their own' to get around MS's lack of support for their old OS's.

In brief, MS does microcode updates too. And aside from the Windows hackers at the above URL, MS gets to decide which versions of their OS's will work 'reliably' (YMMV) on which Intel processors. If your BIOS doesn't have the proper microcode update then Windows may not even boot!

See Your computer stops responding when you restart to complete the installation of Windows XP Service Pack 2 or Windows XP Tablet PC Edition 2005

The moral of the story? Keep your microcode up to date (either in the BIOS or in the OS) or your system (Win/Linux/?) may get flaky/broken due to a change in software. A BIOS update would be best, since it goes into place before the OS hits the silicon. The microcode update utility is more of a stopgap affair; not the perfect solution, but better than nothing. If your BIOS/Mobo manufacturer drops the ball, this may save your bacon.

And now, back to your regularly scheduled Linux programming!   :Laughing: 

----------

## nichocouk

```
$ dmesg | tail

microcode: CPU0 updated from revision 0x1a to 0x2f, date = 08112004

microcode: CPU1 updated from revision 0x1a to 0x2f, date = 08112004

```

Now here is the fun part...

BEFORE:

```

processor       : 0

vendor_id       : GenuineIntel

cpu family      : 15

model           : 2

model name      : Mobile Intel(R) Pentium(R) 4     CPU 3.06GHz

stepping        : 9

cpu MHz         : 1603.799

cache size      : 512 KB

physical id     : 0

siblings        : 2

core id         : 0

cpu cores       : 1

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 2

wp              : yes

flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe cid xtpr

bogomips        : 3209.48

processor       : 1

vendor_id       : GenuineIntel

cpu family      : 15

model           : 2

model name      : Mobile Intel(R) Pentium(R) 4     CPU 3.06GHz

stepping        : 9

cpu MHz         : 1603.799

cache size      : 512 KB

physical id     : 0

siblings        : 2

core id         : 0

cpu cores       : 1

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 2

wp              : yes

flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe cid xtpr

bogomips        : 3206.82

```

After:

```
processor       : 0

vendor_id       : GenuineIntel

cpu family      : 15

model           : 2

model name      : Mobile Intel(R) Pentium(R) 4     CPU 3.06GHz

stepping        : 9

cpu MHz         : 3074.166

cache size      : 512 KB

physical id     : 0

siblings        : 2

core id         : 0

cpu cores       : 1

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 2

wp              : yes

flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe cid xtpr

bogomips        : 6150.22

processor       : 1

vendor_id       : GenuineIntel

cpu family      : 15

model           : 2

model name      : Mobile Intel(R) Pentium(R) 4     CPU 3.06GHz

stepping        : 9

cpu MHz         : 3074.166

cache size      : 512 KB

physical id     : 0

siblings        : 2

core id         : 0

cpu cores       : 1

fdiv_bug        : no

hlt_bug         : no

f00f_bug        : no

coma_bug        : no

fpu             : yes

fpu_exception   : yes

cpuid level     : 2

wp              : yes

flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe cid xtpr

bogomips        : 6146.38

```

Or in other words:

```

$ diff cpu_before cpu_after

7c7

< cpu MHz               : 1603.799

---

> cpu MHz               : 3074.166

22c22

< bogomips      : 3209.48

---

> bogomips      : 6150.22

30c30

< cpu MHz               : 1603.799

---

> cpu MHz               : 3074.166

45c45

< bogomips      : 3206.82

---

> bogomips      : 6146.38

```

 :Laughing: 

----------

## Deepu Sudhakar

Oh haha....does it mean that microcode updating is not as foolproof as it seems?

----------

## devsk

He got correct values for CPU Mhz after the microcode update, what's wrong with that?

----------

## Deepu Sudhakar

 *devsk wrote:*   

> He got correct values for CPU Mhz after the microcode update, what's wrong with that?

 Ooops....didn't notice that. I thought he was pointing out that it messed up his readings or something. My bad.

----------

## zxy

On pentium II celeron (Mendocino) nothing happened, not even a line in dmesg.

----------

## Motormouz

I also got nothing in the dmesg on a quad Pentium III Xeon. Does anybody know why?

----------

## nichocouk

Have you done

```
# rc-update add microcode_ctl boot

# /etc/init.d/microcode_ctl start

```

and do you have 

```
CONFIG_MICROCODE=y
```

----------

## Motormouz

Sorry, I should have looked better. The dmesg reports:

microcode_ctl: writing microcode (length: 249856)

microcode_ctl: microcode successfuly written to /dev/cpu/microcode

Th kernel config is ok.

The line I'm missing is something like: updated version x to version y.

----------

## kernelOfTruth

pretty old thread but IMO it's not worth it opening up a new one:

thanks for the howto  :Smile: 

 *Quote:*   

> cat /proc/cpuinfo 
> 
> processor	: 0
> 
> vendor_id	: GenuineIntel
> ...

 

 *Quote:*   

> [    0.714289] microcode: CPU0 sig=0x106e5, pf=0x2, revision=0x3
> 
> [    0.714374] microcode: CPU1 sig=0x106e5, pf=0x2, revision=0x3
> 
> [    0.714459] microcode: CPU2 sig=0x106e5, pf=0x2, revision=0x3
> ...

 

 *Quote:*   

> [ 4538.462393] microcode: CPU0 updated to revision 0x5, date = 2011-09-01
> 
> [ 4538.463298] microcode: CPU1 updated to revision 0x5, date = 2011-09-01
> 
> [ 4538.464118] microcode: CPU2 updated to revision 0x5, date = 2011-09-01
> ...

 

----------

## jasn

Thanks for pinging the thread. Ever since watching the SystemRescueCD system boot, I've wondered where the Intel microcode update message comes from, and now I've got it enabled on my system, Intel(R) Core(TM) i7-2820QM CPU @ 2.30GHz. BTW, I got the following message when running the update service;

```
[ 1858.131481] microcode: CPU0 updated to revision 0x28, date = 2012-04-24

[ 1858.131994] microcode: CPU1 updated to revision 0x28, date = 2012-04-24

[ 1858.132508] microcode: CPU2 updated to revision 0x28, date = 2012-04-24

[ 1858.133021] microcode: CPU3 updated to revision 0x28, date = 2012-04-24

[ 1858.133507] microcode: CPU4 updated to revision 0x28, date = 2012-04-24

[ 1858.134007] microcode: CPU5 updated to revision 0x28, date = 2012-04-24

[ 1858.134514] microcode: CPU6 updated to revision 0x28, date = 2012-04-24

[ 1858.135024] microcode: CPU7 updated to revision 0x28, date = 2012-04-24

[ 1858.135028] perf_event_intel: PEBS enabled due to microcode update
```

The only thing that's not current with the OP, is that apparently www.urbanmyth.org is no longer providing the homepage for this utility. No problem as the gentoo ebuild, sys-apps/microcode-data-20120606, downloaded the update file from distfiles.gentoo.org.

Thanks..

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## PaulBredbury

The latest is:

http://downloadcenter.intel.com/confirm.aspx?httpDown=http://downloadmirror.intel.com/21925/eng/microcode-20120606-v2.tgz&lang=eng&Dwnldid=21925&keyword=microcode

at:

http://downloadcenter.intel.com/SearchResult.aspx?lang=eng&keyword=microcode

Note that "-v2". This is dated 1-Oct-2012, just to confuse us.

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