# Getting EIST to work: ACPI, DSDT modification

## jannis

Hello,

I got myself an Intel SS4200. The CPU shipped is a Celeron 420 (single core, 1.6GHz, No EIST). Since I wanted to save power, I got an Core 2 Duo E4500 (dual core, 2.2GHz, WITH EIST). The CPU works (system is much faster now) but EIST (Intel Enhanced SpeedStep) is not working since the BIOS does not support it (Why should it? The shipped CPU can't to SpeedStep and CPU replacement is not supported). BIOS-update can't be done since there is no updated BIOS-file available (and never will be).

I've been in the BIOS setup screen. Processor page shows correct information but there is just nothing about EIST there.

After some search on the internet, I found some websites that show how to enable EIST by modifying the ACPI DSDT (I know this is not supported and such ...), most of them hackintosh-pages, but there are some good ones I read:

http://pat.erley.org/Other/P4EISTSSDT

http://www.ztex.de/misc/c2ctl.e.html

and some posts here on this forum related to this topic. I got this far: acpi-cpufreq detects two P-States I defined by modifying the DSDT. cpufreq-info (and the related files under /sys) show the two frequencies, but cpufreq-info says the frequency is still at 2.2GHz. So I thought I might find some ACPI-gurus here that could help.

I also tried to enable C-states as said in the first URL. They then appear in /sys/devices/system/cpu/cpu0.... but the system's power usage is 20 W higher (I got an power meter on the primary side of the system's power supply). So i reverted that change. Can't see my C-states now in /sys but power usage is lower.

The original (unmodified) DSDT is here:

http://paste.pocoo.org/show/331644/

Here is my first try:

http://paste.pocoo.org/show/331645/

And here the second one (both have the same results described above):

http://paste.pocoo.org/show/331646/

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## s0be

One step at a time...

Does C2D support HT?  If so, is it the same HT a P4 uses, or the improved version?

You should either disable hyperthreading and drop CPUs 3,4 add the _PSD/_PSS/_PCT methods to all 4 CPUs.  

I haven't looked at C2D Cpu spec sheets, but are the CPUFREQ changes  coupled between the two cores?  If so, all 4 (2 Physical, 2 HT) cores should share the same _PSD definition.  

That should help with the P-States.

As far as C-States go, I didn't see a single _CST method in any of your posted links, but that should wait until you have all the P-States working that you expect.  After making ^ those changes ^, a dmesg of the newly booting kernel would also help.  Note, I have always had to force acpi-cpufreq to load with a forced dsdt/ssdt.

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## jannis

First: thanks for the answer  :Smile: 

 *s0be wrote:*   

> Does C2D support HT?  If so, is it the same HT a P4 uses, or the improved version?
> 
> You should either disable hyperthreading and drop CPUs 3,4 add the _PSD/_PSS/_PCT methods to all 4 CPUs.

 

The E4500 doesn't support hyperthreading but does have 2 physical cores. The lines about the 3rd and 4th core haven't been added by me, they were in the unmodified DSDT and I didn't remove them. But it is a good hint that I add the P-states to all 4 cores (allthough I only have 2) or just drop the two lines. Never thought about it that way.

 *s0be wrote:*   

> I haven't looked at C2D Cpu spec sheets, but are the CPUFREQ changes  coupled between the two cores?  If so, all 4 (2 Physical, 2 HT) cores should share the same _PSD definition.

 

At least on the Core 2 Duo T5500 I have in my laptop (that also uses the 945G chipset, but the mobile version), the two cores can be in different P-states, they are not linked. That's why I left away the _PSD field. But I also tried with  :Smile: 

 *s0be wrote:*   

> As far as C-States go, I didn't see a single _CST method in any of your posted links, but that should wait until you have all the P-States working that you expect.  After making ^ those changes ^, a dmesg of the newly booting kernel would also help.  Note, I have always had to force acpi-cpufreq to load with a forced dsdt/ssdt.

 

I didn't take a closer look at the C-states since I also tried to do it the "one step at a time"-way and wanted to get the P-states working first. One main difference is that the SS4200 has an ICH7-based chipset and I didn't bother to lookup the correct addresses used for the C-states. Taking a short look into the datasheet they seem to have moved them around, so I removed the C-state thing again.

I'll do some more tests tomorrow, gotta go to bed now

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## jannis

Okay, I got a big step forward (After reading the ACPI-Spec (chapter 8.4.4), the data sheet for the Core 2 Duo E4500, parts of the "Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A" and 3B and the "Enhanced Intel® SpeedStep® Technology for the Intel® Pentium® M Processor" white paper.

The problem is the IA32_MISC_ENABLE (0x01A0) MSR. Bit 16 there is used to dis-/enable Enhanced SpeedStep. This bit is 0 on my machine (EIST off) and cannot be set to 1 using wrmsr (wrmsr exit code is 0 but the read directly after shows the bit is still 0).

The white paper says: Enhanced Intel SpeedStep Technology is enabled by setting the IA32_MISC_ENABLE MSR, bit 16. This bit should be written by the system BIOS upon boot."

Anyone got an idea why it can't be set at any later time? Can't find anything in the datasheets  :Sad: 

Or better: Can I set the bit to 1 using a statement in the DSDT?

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## gidi

 *s0be wrote:*   

> As far as C-States go, I didn't see a single _CST method in any of your posted links, but that should wait until you have all the P-States working that you expect.  After making ^ those changes ^, a dmesg of the newly booting kernel would also help.  Note, I have always had to force acpi-cpufreq to load with a forced dsdt/ssdt.

 

I didn't take a closer look at the C-states since I also tried to do it the "one step at a time"-way and wanted to get the P-states working first. One main difference is that the SS4200 has an ICH7-based chipset and I didn't bother to lookup the correct addresses used for the C-states. Taking a short look into the datasheet they seem to have moved them around, so I removed the C-state thing again.

I'll do some more tests tomorrow, gotta go to bed now

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The SS4200 has a ICH7R which I think to remember does only C1, only the mobile version does more C-States.

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